INTERLINE DYNAMIC VOLTAGE RESTORER PDF

INTERLINE DYNAMIC VOLTAGE RESTORER PDF

Then a new device which is named Inter-line Dynamic Voltage Restorer (IDVR) is discussed. This device consists of two conventional DVRs which are installed. An interline dynamic voltage restorer (IDVR) is a novel c o m p e n s a t i o n piece of mitigation It is made of several dynamic voltage restorers (DVRs) with a. Index Terms—Dynamic voltage restorer, Interline dynamic voltage restorer, Current source inverter, SMES and Power quality.

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Instead of bypassing the DVRs in normal conditions, this paper proposes operating the DVRs, if needed, to improve the displacement factor DF of one of the involved feeders.

Interline dynamic voltage restorer (IDVR) Archives – ASOKA TECHNOLOGIES

Winter Meetingvol. Interine this technique, the source voltages are sensed continuously and when the voltage sag is detected, the shunt reactances are switched into the circuit and decrease the load power factors to improve IDVR performance.

The real and reactive powers are calculated in real time in the tracking loop to achieve better conditions. Dynanic IDVR merely consists of several dynamic voltage restorers DVRs sharing a common dc link connecting independent feeders to secure electric power to critical loads.

It also increases compensation time by operating in minimum active power mode through a controlled transition once the phase jump is compensated. The performance of proposed method is evaluated using simulation study.

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This technique results in less energy being taken out of the DC-link capacitor, resulting in smaller size requirements. The overall three-phase voltage signals during in-phase compensation simulation.

This technical merit demonstrates that DVRs could cover a wider range of voltage sags; the practicality of this idea for better utilization is better than that of existing installed DVRs.

While one of the DVRs compensates for the local voltage sag voltagf its feeder, the other DVRs replenish the common dc-link voltage.

Transient analysis of interline dynamic voltage restorer using dynamic phasor representation

Finally, the simulation and inferline results on the CHB based IDVR confirmed the effectiveness of the proposed configuration and control scheme. It is clear from both the simulation and experimental results illustrated in this paper that the proposed zero-real power tracking technique applied to DVR-based compensation can result in superior performance compared to the traditional in-phase technique.

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The existing control strategies either mitigate the phase jump or improve the utilization of dc link energy by i reducing the amplitude of injected voltage, or ii optimizing the dc bus energy support.

During sag period, active power can be transferred from a feeder to another one and voltage sags with long durations can be mitigated. Computer planning and simulation of power systems require system components to be represented mathematically. Per-phase simulation results for imterline sag condition at: This study aims to enhance the abilities of DVRs to maintain acceptable voltages and last iinterline during compensation.

The main conclusions of this work can be summarized as follows:. The higher active power requirement associated with voltage phase jump compensation has caused a substantial rise in size and cost of dc link energy storage system of DVR. DF improvement resrorer be achieved via active and reactive power exchange PQ sharing between different feeders. In this paper, a new configuration has been proposed which not only improves the compensation capacity of voltahe IDVR at high power factors, but also increases the performance of the compensator to mitigate deep sags at fairly moderate power factors.

Restoerr paper presents a utilization technique for enhancing the capabilities of dynamic voltage restorers DVRs. The results from both the simulation and experimental tests illustrate that the proposed technique clearly achieved superior performance.

In this paper, an enhanced sag compensation strategy is proposed that mitigates the phase jump in the load voltage while improving the overall sag compensation time. Single line diagram of an IPFC in transmission system. Electronics Nuclear engineering, Electrical and Electronic Engineering.

Then, experimental results on a scaled-down IDVR are presented to confirm the theoretical and simulation results. Per-phase experimental and corresponding simulation results for Lnterline improvement case: Both the magnitude and phase displacement angle of the synthesized DVR voltage are precisely adjusted to achieve lower power utilization. The DF of the sourcing feeder increases while the DF of the receiving feeder decreases.

To overcome this limitation, a new idea is presented in this paper which allows to reduce the load power factor under sag condition, and therefore, the compensation vpltage is increased.

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Strathprints home Open Access Login. With the traditional in-phase technique, the compensation was performed and depended on the real power injected to the system.

With this technique, none or less of the real power will be transferred to the system, which provides more for the DVR to cover a wider range of interkine sags, adding more flexible adaptive control to the solution of sag voltage disturbances. The vlotage strategy improves the voltage quality of sensitive loads by protecting them against the grid voltage sags involving the phase jump. In this case, the DF of the sourcing feeder will have a notable improvement with only a slight variation in DF of the receiving feeder.

These operational constraints have been identified and considered.

This paper proposes a new operational mode for the IDVR to improve the DF of different feeders under normal operation. Abojlala, Khaled Issa and Holliday, Derrick and Xu, Lie Transient analysis of interline dynamic voltage restorer using dynamic phasor representation.

The ensure compatibility with transient stability programs, the analysis is performed for the fundamental frequency only, with other frequency components being truncated and without considering harmonics. In this paper an enhanced sag compensation scheme is proposed for capacitor supported DVR.

Investigating the IDVR performance when the proposed method is applied for a sag with depth of 0. To illustrate the effectiveness of the proposed method an analytical comparison is carried out with the existing phase jump compensation schemes. The overall three-phase voltage signals during zero-real power tracking compensation simulation. These advantages were achieved by decreasing the load power factor during sag condition. The main conclusions redtorer this work can be summarized as follows: Further extension in compensation time can be achieved for intermediate sag depths.

This enhancement can also be seen as a considerable reduction in dc link capacitor size for new installation. Mathematical analysis is carried out for each individual component of the IDVR as modular models, which are then aggregated to generate the final model.